Monday, 03:40 GST. Third rewrite of the reward function on my Solana sentiment agent โ the overfitting again, the same six weeks of sideways tape โ when a broker I'd pinged two weeks earlier finally answered. I'd asked for 4nm wafer starts, priced for a small prover farm I've been sketching since the ZK-rollup prototype days. His reply was four words: "4nm is full." Not tight. Full.
That line is worth more than most of the research I read last month, because it inverts the story the market tells itself about Samsung.
The feed narrative is uniform: Samsung Foundry is losing. 2nm contracts slipping, Google's Tensor G5 defecting to TSMC, Taylor pushed. All of it true. And yet SF4 is running somewhere above 85% โ past the healthy-band floor โ while the node everyone wants to discuss sits half-empty. The dumbbell is the story: mature-advanced sold out, most-advanced idle, and almost nobody pricing that asymmetry into anything.
Samsung is not a pure foundry. Memory, System LSI, foundry, handsets โ one balance sheet. Foundry has spent a decade as the recipient of counter-cyclical memory subsidies, and that single structural fact explains everything downstream. TSMC prices to margin; Samsung prices to share, because the memory upcycle pays the difference. In 2024 that buffer absorbed an estimated 2-3 trillion KRW of foundry operating loss. My number for 2025 is 1-2 trillion โ narrowing, not turning. Anyone reading "improved profitability" as a turn is reading a direction, not a signal.
The technology isn't the problem. Samsung shipped GAA nanosheets โ MBCFET โ on SF3 in June 2022, roughly three years before TSMC's N2 flips to nanosheet in Q4 2025. Intel's 18A runs RibbonFET plus backside power. On a node timeline Samsung is not behind; it is early. The gap is commercial maturity โ 1-2 years, 1-1.5 node-equivalents โ and it lives in yield, IP breadth and packaging, not in the transistor.
Yield first, because it's the causal chain nobody prints. SF4 launched at 35-50% and Korean press puts it above 70% in 2025. That crossing of the economic-viability line is the technical precondition for "full" โ you cannot fill a fab on a node that bleeds money per wafer. SF3 launched at 20-30% and sits near 50-60%. SF2 is rumored at 50-60% and needs 12-18 months to reach 65-70% before an Apple-tier or Qualcomm-tier customer signs. TSMC's N4/N5 mature at 80-90%+; N2 initial 60-70%. That delta is the contract delay.
The rest of the node mix is uglier than the headline. SF5 is the awkward one โ underutilized, still hunting new customers, which is what a node in the dead zone between "cheap enough" and "advanced enough" looks like. SF3's customer list is short: Exynos 2500 and little else. Net foundry utilization I'd put at 75-80%, below the top of the healthy band, with 2nm adding idle capacity in H2 2025.
Now the part that decides the AI-ASIC orders, and it isn't the node. Packaging. Samsung has I-Cube for 2.5D and X-Cube for 3D, and the technology is real. The capacity isn't. TSMC's CoWoS output runs on the order of 600-700k wafer-equivalents a year; Samsung's is a rounding error against it. Inference silicon needs 2.5D almost universally, and buyers want leading edge plus CoWoS as one purchase order. Samsung can sell you a 2nm wafer and cannot sell you the package around it โ which means the 2nm contract conversation was never only about 2nm.
Two more silent variables. EUV tool count: I'd put Samsung at 50-60 units against TSMC's 80-100+, which caps multi-patterning throughput before yield even enters the room. Samsung did take an EXE:5000 High-NA unit in 2024 as a first-wave ASML customer โ ahead of TSMC's preference to wait โ but ASML ships maybe 5-10 High-NA machines a year, and three foundries are bidding for them. That's a scheduling war, not a technology war. And SAFE versus OIP: Samsung's IP and EDA partner ecosystem is roughly an order of magnitude narrower than TSMC's, which is what "design-asset validation takes time" actually means. When the algorithm breaks, we become the hedge โ the constraint was never the lithography. It was everything a customer needs around the lithography.
The supply-chain math is boring and decisive. ASML holds a 100% lock on EUV; etch and deposition come from Applied, Lam and TEL; high-end photoresist from JSR and Shin-Etsu; large wafers from Shin-Etsu and SUMCO; EDA from Synopsys, Cadence and Siemens with no real substitute. Samsung is Korean and US-aligned, so there's no export-control wall in front of it. The risk is cadence, not cutoff. EUV lead times run 12-18 months, and a 2nm fab needs 12-24 months from tool move-in to volume. Run that forward: Taylor move-in in H1 2026 puts qualification in H2 2026 at the earliest and full ramp in 2027-2028.
Capex tells the same story in Korean won. 2025 group capex lands around 40-50 trillion KRW, with foundry taking an estimated 15-20 trillion. Against TSMC's 35-45% capex-to-revenue band, Samsung's foundry is high-spend, low-output โ a bleeding phase by design, funded by memory. Taylor alone is ~$37B for 20k wspm, roughly $1.85B per 10k wspm of capital density, with $4.745B of US subsidy attached. Five-to-seven-year straight-line depreciation on that drags 5-10 points off gross margin before a single wafer ships. Break-even needs utilization โฅ90% and ASP recovery of 10-15%. Arbitrage is just patience wearing a speed suit โ and this one is a 2027-2028 trade, not a 2025 trade.
Here's where I part company with the tape.
First, "4nm is full" is not the same as "4nm demand is strong." HBM4's base die is a logic die, and Samsung is supplying it from its own 4nm. Stack Exynos and System LSI internal orders on top, and a meaningful slice of that utilization is captive transfer volume โ group demand dressed as market demand. The silence on customer mix is the tell. External wins get itemized. Internal ones get aggregated.
Second, "not every chip needs the leading edge" is a defensive narrative, not an industry law. It is the sentence you write when your 2nm can't clear a qualification gate. Watch the substitution: if this were a genuine market-structure shift, Samsung wouldn't simultaneously be described as retreating to 4nm and 5nm to fix profitability. That's a fighting withdrawal, not a strategy.
Third, price. Samsung quotes 10-30% under TSMC. Full utilization at a discount is a concession wearing a demand costume: utilization up, pricing power flat. Tesla's $16.5B AI5/AI6 contract, signed July 2025, requires domestic production โ so the real negotiating chip in the 2nm talks was a Taylor schedule promise, not a yield number. Scanning the mempool for ghosts in the machine, the ghost here is the assumption that full fabs mean pricing power. They don't. They mean someone blinked.
What I'm watching, in order: Taylor tool move-in timing in H1 2026; Tesla AI6 tape-out confirmation; the HBM4 base-die ramp split between captive and external; and any CoWoS-equivalent capacity announcement, because that is the only number that changes the AI-ASIC math. Until then, treat foundry utilization as a leading indicator for decentralized compute pricing, not for Samsung's multiple. Every bug is a bounty waiting for the right eyes. This one is sitting in a utilization table, and the market is still reading the headline.